Frequency doubling circuits are commonly used to generate a frequency doubled output signal having a frequency twice that of an input (or reference) signal. Various frequency doubling circuits are discussed, for example, in the following U.S. Patents: U.S. Pat. No. 5,475,349 to Cohn entitled "Frequency Multipliers Using Diode Arrays"; U.S. Pat. No. 5,194,820 to Besson et al. entitled "Frequency Doubling Device"; U.S. Pat. No. 4,691,170 to Riley entitled "Frequency Multiplier Circuit"; U.S. Pat. No. 5,365,181 to Mair entitled "Frequency Doubler Having Adaptive Biasing"; U.S. Pat. No. 4,048,571 to Jacobson entitled "Frequency Doubler"; U.S. Pat. No. 4,734,591 to lchitsubo entitled "Frequency Doubler"; and U.S. Pat. No. 5,552,734 to Kimura entitled "Local Oscillator Frequency Multiplier And Mixing Circuitry Comprising a Squaring Circuit". Each of these patents is hereby incorporated herein in its entirety by reference.
It is known, for example, to double the frequency of a reference signal A using a delay circuit 21 and an Exclusive-OR gate 23 as shown in FIGS. 1 and 2. In particular, the digital reference signal A is delayed by a period of time .tau. to generate the delayed signal B. The reference signal A can have rising edges occurring at times Tr and falling edges at times Tf. The resulting delayed signal B can thus have rising edges at times Tr+.tau. and the falling edges at times Tf+.tau.. Accordingly, the output of the Exclusive-OR gate 23 can have a logical 1 output during the time intervals from Tr to Tr+.tau., and from Tf to Tf+.tau., and the output of the Exclusive-OR gate 23 can have a logical 0 output during the remainder of the time when the reference signal A and the delayed signal B are both either high or low. In other words, the output signal C generated by the Exclusive-OR gate 23 will have two pulses of duration .tau. for each period of the reference signal A in effect providing an output frequency twice that of the reference signal.
In the circuit of FIG. 1, however, it may be difficult to provide an output signal C having a 50% duty cycle. In particular, the duty cycle of the output signal C is dependent on the duration of the delay .tau. provided by the delay circuit 21, and the duration of the delay .tau. may be difficult to precisely control. If a delay .tau. can be one quarter of the period (T/4) of the reference signal A, the output signal will have a 50% duty cycle. Desired accuracies may be difficult to provide, however, because of the difficulty of providing low tolerance components such as capacitors and resistors to build a delay circuit.
For example, resistors and capacitors may both be subject to semiconductor manufacturing process fluctuations resulting in 3.sigma. tolerances as great as .+-.20%. Because the delay that is implemented depends on the RC product, the combined tolerance for the delay may be on the order of .+-.40%. In other words, a designed delay of 0.25 T may have process tolerance extremes of 0.16 T and 0.36 T resulting in duty cycle extremes of 32% and 72% which are significantly different from 50% (where T is the period of the reference signal).
When providing a frequency doubled output signal for a Radio Frequency (RF) mixer in the signal path of a radio communications transceiver, an accurate 50% duty cycle may be important to suppress even order intermodulation products. Accordingly, a bandpass filter may be needed at the output of the Exclusive-OR gate 23 to suppress even order harmonics of the frequency doubled output signal C thus adding circuitry. Furthermore, suitable bandpass filters may be difficult to implement on an integrated circuit device thereby increasing the size of the system including the frequency doubling circuit and filters.
In addition, the frequency doubled output signal is often used in a differential form in Radio Frequency (RF) integrated circuit applications. Such a differential form can be provided using the circuit illustrated in FIG. 3 including delay circuits 31 and 33 and Exclusive-OR gates 35 and 37. The circuit of FIG. 3 is essentially the combination of two FIG. 1 circuits being driven by a reference signal D and its inverse D-bar. This circuit, however, is subject to the same difficulties in providing a 50% duty cycle discussed above with regard to FIG. 1. In addition, the two delay circuits 31 and 33 should be closely matched to provide outputs that are truly differential. The desired matching, however, may be difficult to achieve.
Accordingly, there continues to exist a need in the art for improved frequency doubling circuits, methods, and systems.